In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases. In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). For example, published International Patent Application No. WO 97/14214, discloses a compensated delay locked loop timing vernier. The disclosed timing vernier produces a set of timing signals of similar frequency and evenly distributed phase. An input reference clock signal is passed through a succession of delay stages. A separate timing signal is produced at the output of each delay stage. The reference clock signal and the timing signal output of the last delay stage are compared by an analog phase lock controller. The analog phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. Based on the results of the oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the “eye.” The phase of the VCDL is adjusted to keep up with phase deviations of the incoming data.
Voltage controlled delay loops often require a clock signal with a controllable phase to peform a number of functions, such as margining and trimming. For example, voltage controlled delay loops employ a number of delay stages that typically employ transistor technology. Such transistors may not be evenly matched, and trimming of the delay stages may be required. Thus, a clock signal with a controllable phase is required to trim each of the delay stages. The phase control function, however, typically introduces nonlinearities and discontinuities into the clock signal that have an adverse effect on the accuracy of the trimming function. A need therefore exists for a clock signal with a controllable phase that exhibits improved linearity and continuity characteristics.